1. Technical Field
The invention relates to a phase shift keying communication system and, more particularly, to a differential phase shift keying system.
2. Description of the Related Art
Two well known phase shift keying communication systems are binary phase shift keying, or BPSK, and differential phase shift keying, or DPSK. Referring to FIG. 1, the encoding scheme for both BPSK and DPSK systems are illustrated with respect to encoding the binary data sequence 1011001. In the case of BPSK, the carrier phase angle (with respect to an arbitrary reference) is 0 if the data bit is 0 and .pi. if the bit is 1. In the case of DPSK, the carrier phase of a given channel symbol is the same as that of the previous symbol if the data bit is 0, and shifted by .pi. with respect to the previous symbol if the data bit is 1. Also, one extra symbol is required at the beginning of each transmission in the DPSK system to provide a phase reference for the first data bit. As seen in FIG. 1A, the data is mapped onto the absolute phase of the channel symbol in the case of BPSK, and the phase shift between adjacent symbols in the case of DPSK. Note that DPSK encodes the input data onto the first difference of the phase between adjacent channel symbols.
In DPSK systems, the performance is sensitive to receiver frequency offsets and thus, automatic frequency control circuits are required. As these circuits usually have long settling times, rapid acquisition is not obtainable, which is particularly problematic for the reception of short data packets. This frequency sensitivity of DPSK is explained in detail in Spilker, J. J., Digital Communication by Satellite, Prentice-Hall, 1977, pp. 331-335. Briefly, the phase shift between adjacent symbols in a received DPSK signal depends not only on the impressed modulation at the transmitter but also on the offset of the received carrier frequency relative to the transmitted carrier frequency (multiplied by the symbol duration).
FIG. 2 shows the block diagram of a prior art DPSK demodulator. The block diagram uses complex baseband signal representation, which assumes the presence of an I/Q-splitting device such as a Hilbert transformer or quadrature downconverter as a preprocessor.
In addition to the binary encoding schemes illustrated by FIGS. 1A and 1B, there are also higher order digital modulation schemes. These are often referred to as M-ary modulation, where M is usually a power of two, e.g. M=4, 8, 16, etc. In M-ary PSK using coherent demodulation, groups of n-bits are collected to form n-bit words. These words then modulate the carrier phase in each channel symbol by selecting one of 2.sup.n possible phases uniformly distributed between 0 and 2 .pi. radians. For example, in quadrature phase shift keying (QPSK), n=2 and the phases selected are 0, .pi./2, .pi. and 3.pi./2, as shown in FIG. 1C. In DQPSK (single-differential quadrature phase shift keying), the phase shifts are selected similarly, but, unlike QPSK which uses coherent demodulation, the reference for each phase shift in DQPSK is the phase of the previous symbol. In QPSK, the reference phase is that of the unmodulated carrier of the transmitter, which has to be regenerated at the receiver.
Several techniques for overcoming the problem of frequency offset sensitivity in DPSK (as well as M-ary differential phase shift keying) have been attempted. In one technique, a pilot signal is transmitted along with the desired signal to facilitate frequency offset estimation at the receiver. If possible, the pilot signal is transmitted in-band with the desired signal so that separate RF/IF sections are not required for reception of the pilot signal. An example of this approach is the HF Kineplex (Navy TADIL-A Link 11) system, where one tone (at 650 Hz) in a multitone, voiceband, differential QPSK system is reserved for Doppler correction as described in Schoppe, W. J., "The Navy's Use of Digital Radio", IEEE Trans. Vol. COM-27, December, 1979. Disadvantageously, use of a separate pilot signal wastes transmitted signal power and violates the constant amplitude signal characteristic, which is desirable in communication systems using nonlinear amplification.
In another known technique, an automatic frequency control feedback loop is used to correct the frequency offset in DPSK. The frequency accuracy requirement is not very critical; the residual frequency offset must be small compared to the inverse of the bit period, as explained in Spilker, J. J., Digital Communications by Satellite, Prentice-Hall, 1977, p. 334. Typical techniques used are FFT and the quadrature component of the output of a complex differential detector, as described in Henley, S. J., "Modem for the Land Mobile Satellite Channel", Conf. Proc., NASA/JPL Mobile Satellite Conference, May 3-5, 1988, JPL Publ. No. 88-9, pp. 323-328. Disadvantageously, in the demodulation of short data bursts, sufficient time may not be available for the AFC loop to reach its steady state. Fast response in the AFC loop, as in any feedback loop, is obtained by widening the loop bandwidth, which results in greater error in the frequency estimate.
It is this deficiency of the closed loop approach that has led to proposals for open loop approaches. A feedforward technique for frequency offset compensation in DPSK demodulation, or the JPL technique, is described in Simon, M. K. and Divsalar, D., "Doppler-Corrected Differential Detection of MPSK", IEEE Transactions on Communications, Vol. 37, No. 2, February 1989, pp. 99-109. Briefly, the JPL technique involves demodulating DPSK with more complex processing than is used for conventional differential detection. The phase error due to frequency offset is estimated by measuring the phase shift at two points in time separated by half the symbol period and situated symmetrically about the center of the symbol period. This phase shift value is measured for each symbol, over many symbols, and the sequence of values is digitally lowpass filtered to minimize the estimation error. The filtered phase shift estimate is then used to correct the phase of the complex signal at the output of the differential detector prior to bit decisions.
The JPL technique involves an averaging period for phase error estimation that spans several symbols, which limits the acquisition speed of this scheme. Performance degradation using the JPL technique for small averaging times can be substantial. For an averaging time equal to the ten symbols, the degradation is approximately 2.5 dB. Moreover, the JPL technique requires substantial amounts of complex processing.
Another technique is shown in U.S. Pat. No. 4,922,206 of Nicholas issued May 1, 1990, entitled "Method of Demodulation Using Split Delay Line" in which phase error due to frequency offset is reduced by using a pair of split delay lines, each of which provides a delay equal to half of the symbol duration. This technique can be considered as a network of three differential detectors. The first stage generates two signals each of which is the result of differential detection across points separated by half the signal duration. The second stage detects the differential between the above two signals. However, this technique does not and cannot use full-symbol integration after the first stage of differential detection because that would require integration across a symbol boundary which could lead to signal cancellation. Accordingly, the noise sensitivity performance is significantly degraded.